Timery

TIM17 0x40014800

19 rejestrów/klastrów w tym peryferium.

Rejestr: CR1 0x40014800

control register 1

Bit	Szer.	Pole	Dostęp	Opis
0	1	CEN	`rw`	Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.
1	1	UDIS	`rw`	Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
2	1	URS	`rw`	Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
3	1	OPM	`rw`	One pulse mode
7	1	ARPE	`rw`	Auto-reload preload enable
8–9	2	CKD	`rw`	Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx),
11	1	UIFREMAP	`rw`	UIF status bit remapping

Rejestr: CR2 0x40014804

control register 2

Bit	Szer.	Pole	Dostęp	Opis
0	1	CCPC	`rw`	Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output.
2	1	CCUS	`rw`	Capture/compare control update selection Note: This bit acts only on channels that have a complementary output.
3	1	CCDS	`rw`	Capture/compare DMA selection
8	1	OIS1	`rw`	Output Idle state (OC1 output)
9	1	OIS1N	`rw`	Output Idle state (OC1N output)

Rejestr: DIER 0x4001480C

DMA/Interrupt enable register

Bit	Szer.	Pole	Dostęp	Opis
0	1	UIE	`rw`	Update interrupt enable
1	1	CC1IE	`rw`	Capture/Compare 1 interrupt enable
5	1	COMIE	`rw`	COM interrupt enable
7	1	BIE	`rw`	Break interrupt enable
8	1	UDE	`rw`	Update DMA request enable
9	1	CC1DE	`rw`	Capture/Compare 1 DMA request enable

Rejestr: SR 0x40014810

status register

Bit	Szer.	Pole	Dostęp	Opis
0	1	UIF	`rw`	Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register.
1	1	CC1IF	`rw`	Capture/compare 1 interrupt flag
5	1	COMIF	`rw`	COM interrupt flag
7	1	BIF	`rw`	Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.
9	1	CC1OF	`rw`	Capture/Compare 1 overcapture flag

Rejestr: EGR 0x40014814

event generation register

Bit	Szer.	Pole	Dostęp	Opis
0	1	UG	`wo`	Update generation This bit can be set by software, it is automatically cleared by hardware.
1	1	CC1G	`wo`	Capture/compare 1 generation
5	1	COMG	`wo`	Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output.
7	1	BG	`wo`	Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.

Rejestr: CCMR1_Input 0x40014818

capture/compare mode register 1 (input mode)

Brak zdefiniowanych pól bitowych.

Rejestr: CCMR1_Output 0x40014818

capture/compare mode register (output mode)

Bit	Szer.	Pole	Dostęp	Opis
0–1	2	CC1S	`rw`	Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER).
0–1	2	CC1S	`rw`	Capture/Compare 1 selection
2	1	OC1FE	`rw`	Output compare 1 fast enable
2–3	2	IC1PSC	`rw`	Input capture 1 prescaler
3	1	OC1PE	`rw`	Output compare 1 preload enable
4–6	3	OC1M	`rw`	Output compare 1 mode
4–7	4	IC1F	`rw`	Input capture 1 filter
16	1	OC1M_3	`rw`	Output compare 1 mode, bit 3

Rejestr: CCER 0x40014820

capture/compare enable register

Bit	Szer.	Pole	Dostęp	Opis
0	1	CC1E	`rw`	Capture/Compare 1 output enable
1	1	CC1P	`rw`	Capture/Compare 1 output Polarity
2	1	CC1NE	`rw`	Capture/Compare 1 complementary output enable
3	1	CC1NP	`rw`	Capture/Compare 1 output Polarity

Rejestr: CNT16 0x40014824

16-bit counter register

Brak zdefiniowanych pól bitowych.

Rejestr: CNT: 0x40014824

counter

Bit	Szer.	Pole	Dostęp	Opis
0–15	16	CNT	`rw`	counter value
0–15	16	CNT	`rw`	counter value
31	1	UIFCPY	`ro`	UIF Copy

Rejestr: PSC 0x40014828

prescaler

Bit	Szer.	Pole	Dostęp	Opis
0–15	16	PSC:	—	Prescaler value

Rejestr: ARR 0x4001482C

auto-reload register

Bit	Szer.	Pole	Dostęp	Opis
0–15	16	ARR:	—	Auto-reload value

Rejestr: RCR 0x40014830

repetition counter register

Bit	Szer.	Pole	Dostęp	Opis
0–7	8	REP:	—	Repetition counter value

Rejestr: CCR1 0x40014834

capture/compare register

Bit	Szer.	Pole	Dostęp	Opis
0–15	16	CCR:	—	Capture/Compare value

Rejestr: BDTR 0x40014844

break and dead-time register

Bit	Szer.	Pole	Dostęp	Opis
0–7	8	DTG	`rw`	Dead-time generator setup
8–9	2	LOCK	`rw`	Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.
10	1	OSSI	`rw`	Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
11	1	OSSR	`rw`	Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
12	1	BKE	`rw`	Break enable 1; Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
13	1	BKP	`rw`	Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
14	1	AOE	`rw`	Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
15	1	MOE	`rw`	Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page846).
16–19	4	BKF	`rw`	Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
26	1	BKDSRM	`rw`	Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
28	1	BKBID	`rw`	Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

Rejestr: DCR 0x40014848

DMA control register

Bit	Szer.	Pole	Dostęp	Opis
0–4	5	DBA	`rw`	DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.
8–12	5	DBL	`rw`	DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ...

Rejestr: DMAR 0x4001484C

DMA address for full transfer

Bit	Szer.	Pole	Dostęp	Opis
0–15	16	DMAB:	—	DMA register for burst accesses

Rejestr: AF1 0x40014860

TIM17 option register 1

Bit	Szer.	Pole	Dostęp	Opis
0	1	BKINE	`rw`	BRK BKIN input enable This bit enables the BKIN alternate function input for the timer's BRK input. BKIN input is 'ORed' with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
1	1	BKCMP1E	`rw`	BRK COMP1 enable This bit enables the COMP1 for the timer's BRK input. COMP1 output is 'ORed' with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
2	1	BKCMP2E	`rw`	BRK COMP2 enable This bit enables the COMP2 for the timer's BRK input. COMP2 output is 'ORed' with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
9	1	BKINP	`rw`	BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
10	1	BKCMP1P	`rw`	BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
11	1	BKCMP2P	`rw`	BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

Rejestr: TISEL 0x40014868

input selection register

Bit	Szer.	Pole	Dostęp	Opis
0–3	4	TI1SEL	`rw`	selects TI1[0] to TI1[15] input Others: Reserved