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SPI3 0x40003C00

10 rejestrów/klastrów w tym peryferium.

Rejestr: CR1:  0x40003C00
Bit 31: zarezerwowany31Bit 30: zarezerwowanyBit 29: zarezerwowanyBit 28: zarezerwowany28Bit 27: zarezerwowanyBit 26: zarezerwowanyBit 25: zarezerwowanyBit 24: zarezerwowany24Bit 23: zarezerwowanyBit 22: zarezerwowanyBit 21: zarezerwowanyBit 20: zarezerwowany20Bit 19: zarezerwowanyBit 18: zarezerwowanyBit 17: zarezerwowanyBit 16: zarezerwowany16Bit 15: BIDIMODEBit 14: BIDIOEBit 13: CRCENBit 12: CRCNEXT12Bit 11: CRCLBit 10: RXONLYBit 9: SSMBit 8: SSI8Bit 7: LSBFIRSTBit 6: SPEBit 5: BRBit 4: BR4Bit 3: BRBit 2: MSTRBit 1: CPOLBit 0: CPHA0
BitSzer.PoleDostępOpis
01CPHA`rw`Clock phase Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied at TI mode.
11CPOL`rw`Clock polarity Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied at TI mode.
21MSTR`rw`Master selection Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode.
3–53BR`rw`Baud rate control Note: These bits should not be changed when communication is ongoing. These bits are not used in I2S mode.
61SPE`rw`SPI enable Note: When disabling the SPI, follow the procedure described in SPI on page1020. This bit is not used in I2S mode.
71LSBFIRST`rw`Frame format Note: 1. This bit should not be changed when communication is ongoing. 2. This bit is not used in I2S mode and SPI TI mode.
81SSI`rw`Internal slave select This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. Note: This bit is not used in I2S mode and SPI TI mode.
91SSM`rw`Software slave management When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. Note: This bit is not used in I2S mode and SPI TI mode.
101RXONLY`rw`Receive only mode enabled. This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. Note: This bit is not used in I2S mode.
111CRCL`rw`CRC length This bit is set and cleared by software to select the CRC length. Note: This bit should be written only when SPI is disabled (SPE = '0') for correct operation. This bit is not used in I2S mode.
121CRCNEXT`rw`Transmit CRC next Note: This bit has to be written as soon as the last data is written in the SPIx_DR register. This bit is not used in I2S mode.
131CRCEN`rw`Hardware CRC calculation enable Note: This bit should be written only when SPI is disabled (SPE = '0') for correct operation. This bit is not used in I2S mode.
141BIDIOE`rw`Output enable in bidirectional mode This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode. Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used. This bit is not used in I2S mode.
151BIDIMODE`rw`Bidirectional data mode enable. This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. Note: This bit is not used in I2S mode.
Rejestr: CR2:  0x40003C04
Bit 31: zarezerwowany31Bit 30: zarezerwowanyBit 29: zarezerwowanyBit 28: zarezerwowany28Bit 27: zarezerwowanyBit 26: zarezerwowanyBit 25: zarezerwowanyBit 24: zarezerwowany24Bit 23: zarezerwowanyBit 22: zarezerwowanyBit 21: zarezerwowanyBit 20: zarezerwowany20Bit 19: zarezerwowanyBit 18: zarezerwowanyBit 17: zarezerwowanyBit 16: zarezerwowany16Bit 15: zarezerwowanyBit 14: LDMA_TXBit 13: LDMA_RXBit 12: FRXTH12Bit 11: DSBit 10: DSBit 9: DSBit 8: DS8Bit 7: TXEIEBit 6: RXNEIEBit 5: ERRIEBit 4: FRF4Bit 3: NSSPBit 2: SSOEBit 1: TXDMAENBit 0: RXDMAEN0
BitSzer.PoleDostępOpis
01RXDMAEN`rw`Rx buffer DMA enable When this bit is set, a DMA request is generated whenever the RXNE flag is set.
11TXDMAEN`rw`Tx buffer DMA enable When this bit is set, a DMA request is generated whenever the TXE flag is set.
21SSOE`rw`SS output enable Note: This bit is not used in I2S mode and SPI TI mode.
31NSSP`rw`NSS pulse management This bit is used in master mode only. it allows the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. It has no meaning if CPHA = '1', or FRF = '1'. Note: 1. This bit must be written only when the SPI is disabled (SPE=0). 2. This bit is not used in I2S mode and SPI TI mode.
41FRF`rw`Frame format 1 SPI TI mode Note: This bit must be written only when the SPI is disabled (SPE=0). This bit is not used in I2S mode.
51ERRIE`rw`Error interrupt enable This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I2S mode).
61RXNEIE`rw`RX buffer not empty interrupt enable
71TXEIE`rw`Tx buffer empty interrupt enable
8–114DS`rw`Data size These bits configure the data length for SPI transfers. If software attempts to write one of the 'Not used' values, they are forced to the value '0111' (8-bit) Note: These bits are not used in I2S mode.
121FRXTH`rw`FIFO reception threshold This bit is used to set the threshold of the RXFIFO that triggers an RXNE event Note: This bit is not used in I2S mode.
131LDMA_RX`rw`Last DMA transfer for reception
141LDMA_TX`rw`Last DMA transfer for transmission
Rejestr: SR:  0x40003C08
Bit 31: zarezerwowany31Bit 30: zarezerwowanyBit 29: zarezerwowanyBit 28: zarezerwowany28Bit 27: zarezerwowanyBit 26: zarezerwowanyBit 25: zarezerwowanyBit 24: zarezerwowany24Bit 23: zarezerwowanyBit 22: zarezerwowanyBit 21: zarezerwowanyBit 20: zarezerwowany20Bit 19: zarezerwowanyBit 18: zarezerwowanyBit 17: zarezerwowanyBit 16: zarezerwowany16Bit 15: zarezerwowanyBit 14: zarezerwowanyBit 13: zarezerwowanyBit 12: FTLVL12Bit 11: FTLVLBit 10: FRLVLBit 9: FRLVLBit 8: FRE8Bit 7: BSYBit 6: OVRBit 5: MODFBit 4: CRCERR4Bit 3: UDRBit 2: CHSIDEBit 1: TXEBit 0: RXNE0
BitSzer.PoleDostępOpis
01RXNE`ro`Receive buffer not empty
11TXE`ro`Transmit buffer empty
21CHSIDE`ro`Channel side Note: This bit is not used in SPI mode. It has no significance in PCM mode.
31UDR`ro`Underrun flag This flag is set by hardware and reset by a software sequence. Refer to page1056 for the software sequence. Note: This bit is not used in SPI mode.
41CRCERR`rw`CRC error flag Note: This flag is set by hardware and cleared by software writing 0. This bit is not used in I2S mode.
51MODF`ro`Mode fault This flag is set by hardware and reset by a software sequence. Refer to (MODF) on page1030 for the software sequence. Note: This bit is not used in I2S mode.
61OVR`ro`Overrun flag This flag is set by hardware and reset by a software sequence. Refer to page1056 for the software sequence.
71BSY`ro`Busy flag This flag is set and cleared by hardware. Note: The BSY flag must be used with caution: refer to and .
81FRE`ro`Frame format error This flag is used for SPI in TI slave mode and I2S slave mode. Refer to error flags and . This flag is set by hardware and reset when SPIx_SR is read by software.
9–102FRLVL`ro`FIFO reception level
11–122FTLVL`ro`FIFO transmission level These bits are set and cleared by hardware. Note: This bit is not used in I2S mode.
Rejestr: DR8  0x40003C0C
rw

Direct 8-bit access to data register

Brak zdefiniowanych pól bitowych.

Rejestr: DR:  0x40003C0C
Bit 31: zarezerwowany31Bit 30: zarezerwowanyBit 29: zarezerwowanyBit 28: zarezerwowany28Bit 27: zarezerwowanyBit 26: zarezerwowanyBit 25: zarezerwowanyBit 24: zarezerwowany24Bit 23: zarezerwowanyBit 22: zarezerwowanyBit 21: zarezerwowanyBit 20: zarezerwowany20Bit 19: zarezerwowanyBit 18: zarezerwowanyBit 17: zarezerwowanyBit 16: zarezerwowany16Bit 15: DRBit 14: DRBit 13: DRBit 12: DR12Bit 11: DRBit 10: DRBit 9: DRBit 8: DR8Bit 7: DRBit 6: DRBit 5: DRBit 4: DR4Bit 3: DRBit 2: DRBit 1: DRBit 0: DR0
BitSzer.PoleDostępOpis
0–78DR:—Data register
0–1516DR`rw`Data register Data received or to be transmitted The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See ). Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used.
Rejestr: CRCPR:  0x40003C10
Bit 31: zarezerwowany31Bit 30: zarezerwowanyBit 29: zarezerwowanyBit 28: zarezerwowany28Bit 27: zarezerwowanyBit 26: zarezerwowanyBit 25: zarezerwowanyBit 24: zarezerwowany24Bit 23: zarezerwowanyBit 22: zarezerwowanyBit 21: zarezerwowanyBit 20: zarezerwowany20Bit 19: zarezerwowanyBit 18: zarezerwowanyBit 17: zarezerwowanyBit 16: zarezerwowany16Bit 15: CRCPOLYBit 14: CRCPOLYBit 13: CRCPOLYBit 12: CRCPOLY12Bit 11: CRCPOLYBit 10: CRCPOLYBit 9: CRCPOLYBit 8: CRCPOLY8Bit 7: CRCPOLYBit 6: CRCPOLYBit 5: CRCPOLYBit 4: CRCPOLY4Bit 3: CRCPOLYBit 2: CRCPOLYBit 1: CRCPOLYBit 0: CRCPOLY0
BitSzer.PoleDostępOpis
0–1516CRCPOLY`rw`CRC polynomial register This register contains the polynomial for the CRC calculation. The CRC polynomial (0x0007) is the reset value of this register. Another polynomial can be configured as required.
Rejestr: RXCRCR:  0x40003C14
Bit 31: zarezerwowany31Bit 30: zarezerwowanyBit 29: zarezerwowanyBit 28: zarezerwowany28Bit 27: zarezerwowanyBit 26: zarezerwowanyBit 25: zarezerwowanyBit 24: zarezerwowany24Bit 23: zarezerwowanyBit 22: zarezerwowanyBit 21: zarezerwowanyBit 20: zarezerwowany20Bit 19: zarezerwowanyBit 18: zarezerwowanyBit 17: zarezerwowanyBit 16: zarezerwowany16Bit 15: RXCRCBit 14: RXCRCBit 13: RXCRCBit 12: RXCRC12Bit 11: RXCRCBit 10: RXCRCBit 9: RXCRCBit 8: RXCRC8Bit 7: RXCRCBit 6: RXCRCBit 5: RXCRCBit 4: RXCRC4Bit 3: RXCRCBit 2: RXCRCBit 1: RXCRCBit 0: RXCRC0
BitSzer.PoleDostępOpis
0–1516RXCRC`ro`Rx CRC register When CRC calculation is enabled, the RXCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPIx_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY Flag is set could return an incorrect value. These bits are not used in I2S mode.
Rejestr: TXCRCR:  0x40003C18
Bit 31: zarezerwowany31Bit 30: zarezerwowanyBit 29: zarezerwowanyBit 28: zarezerwowany28Bit 27: zarezerwowanyBit 26: zarezerwowanyBit 25: zarezerwowanyBit 24: zarezerwowany24Bit 23: zarezerwowanyBit 22: zarezerwowanyBit 21: zarezerwowanyBit 20: zarezerwowany20Bit 19: zarezerwowanyBit 18: zarezerwowanyBit 17: zarezerwowanyBit 16: zarezerwowany16Bit 15: TXCRCBit 14: TXCRCBit 13: TXCRCBit 12: TXCRC12Bit 11: TXCRCBit 10: TXCRCBit 9: TXCRCBit 8: TXCRC8Bit 7: TXCRCBit 6: TXCRCBit 5: TXCRCBit 4: TXCRC4Bit 3: TXCRCBit 2: TXCRCBit 1: TXCRCBit 0: TXCRC0
BitSzer.PoleDostępOpis
0–1516TXCRC`ro`Tx CRC register When CRC calculation is enabled, the TXCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY flag is set could return an incorrect value. These bits are not used in I2S mode.
Rejestr: I2SCFGR:  0x40003C1C
Bit 31: zarezerwowany31Bit 30: zarezerwowanyBit 29: zarezerwowanyBit 28: zarezerwowany28Bit 27: zarezerwowanyBit 26: zarezerwowanyBit 25: zarezerwowanyBit 24: zarezerwowany24Bit 23: zarezerwowanyBit 22: zarezerwowanyBit 21: zarezerwowanyBit 20: zarezerwowany20Bit 19: zarezerwowanyBit 18: zarezerwowanyBit 17: zarezerwowanyBit 16: zarezerwowany16Bit 15: zarezerwowanyBit 14: zarezerwowanyBit 13: zarezerwowanyBit 12: ASTRTEN12Bit 11: I2SMODBit 10: I2SEBit 9: I2SCFGBit 8: I2SCFG8Bit 7: PCMSYNCBit 6: zarezerwowanyBit 5: I2SSTDBit 4: I2SSTD4Bit 3: CKPOLBit 2: DATLENBit 1: DATLENBit 0: CHLEN0
BitSzer.PoleDostępOpis
01CHLEN`rw`Channel length (number of bits per audio channel) The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. Note: For correct operation, this bit should be configured when the I2S is disabled. It is not used in SPI mode.
1–22DATLEN`rw`Data length to be transferred Note: For correct operation, these bits should be configured when the I2S is disabled. They are not used in SPI mode.
31CKPOL`rw`Inactive state clock polarity Note: For correct operation, this bit should be configured when the I2S is disabled. It is not used in SPI mode. The bit CKPOL does not affect the CK edge sensitivity used to receive or transmit the SD and WS signals.
4–52I2SSTD`rw`I2S standard selection For more details on I2S standards, refer to Note: For correct operation, these bits should be configured when the I2S is disabled. They are not used in SPI mode.
71PCMSYNC`rw`PCM frame synchronization Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used). It is not used in SPI mode.
8–92I2SCFG`rw`I2S configuration mode Note: These bits should be configured when the I2S is disabled. They are not used in SPI mode.
101I2SE`rw`I2S enable Note: This bit is not used in SPI mode.
111I2SMOD`rw`I2S mode selection Note: This bit should be configured when the SPI is disabled.
121ASTRTEN`rw`Asynchronous start enable. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and an appropriate transition is detected on the WS signal. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and the appropriate level is detected on the WS signal. Note: The appropriate transition is a falling edge on WS signal when I2S Philips Standard is used, or a rising edge for other standards. The appropriate level is a low level on WS signal when I2S Philips Standard is used, or a high level for other standards. Please refer to for additional information.
Rejestr: I2SPR:  0x40003C20
Bit 31: zarezerwowany31Bit 30: zarezerwowanyBit 29: zarezerwowanyBit 28: zarezerwowany28Bit 27: zarezerwowanyBit 26: zarezerwowanyBit 25: zarezerwowanyBit 24: zarezerwowany24Bit 23: zarezerwowanyBit 22: zarezerwowanyBit 21: zarezerwowanyBit 20: zarezerwowany20Bit 19: zarezerwowanyBit 18: zarezerwowanyBit 17: zarezerwowanyBit 16: zarezerwowany16Bit 15: zarezerwowanyBit 14: zarezerwowanyBit 13: zarezerwowanyBit 12: zarezerwowany12Bit 11: zarezerwowanyBit 10: zarezerwowanyBit 9: MCKOEBit 8: ODD8Bit 7: I2SDIVBit 6: I2SDIVBit 5: I2SDIVBit 4: I2SDIV4Bit 3: I2SDIVBit 2: I2SDIVBit 1: I2SDIVBit 0: I2SDIV0
BitSzer.PoleDostępOpis
0–78I2SDIV`rw`I2S linear prescaler I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values. Refer to . Note: These bits should be configured when the I2S is disabled. They are used only when the I2S is in master mode. They are not used in SPI mode.
81ODD`rw`Odd factor for the prescaler Refer to . Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. It is not used in SPI mode.
91MCKOE`rw`Master clock output enable Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. It is not used in SPI mode.