System
FLASH 0x40022000
11 rejestrów/klastrów w tym peryferium.
Rejestr: ACR 0x40022000
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Access control register
| Bit | Szer. | Pole | Dostęp | Opis |
| 0–2 | 3 | LATENCY: | — | Latency |
| 8 | 1 | PRFTEN: | — | Prefetch enable |
| 9 | 1 | ICEN: | — | Instruction cache enable |
| 11 | 1 | ICRST: | — | Instruction cache reset |
| 16 | 1 | EMPTY: | — | Flash User area empty |
Rejestr: KEYR 0x40022008
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Flash key register
| Bit | Szer. | Pole | Dostęp | Opis |
| 0–31 | 32 | KEY: | — | KEYR |
Rejestr: OPTKEYR 0x4002200C
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Option byte key register
| Bit | Szer. | Pole | Dostęp | Opis |
| 0–31 | 32 | OPTKEY: | — | Option byte key |
Rejestr: SR 0x40022010
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Status register
| Bit | Szer. | Pole | Dostęp | Opis |
| 0 | 1 | EOP: | — | End of operation |
| 1 | 1 | OPERR: | — | Operation error |
| 3 | 1 | PROGERR: | — | Programming error |
| 4 | 1 | WRPERR: | — | Write protected error |
| 5 | 1 | PGAERR: | — | Programming alignment error |
| 6 | 1 | SIZERR: | — | Size error |
| 7 | 1 | PGSERR: | — | Programming sequence error |
| 8 | 1 | MISSERR: | — | Fast programming data miss error |
| 9 | 1 | FASTERR: | — | Fast programming error |
| 15 | 1 | OPTVERR: | — | Option and Engineering bits loading validity error |
| 16 | 1 | BSY1: | — | BSY1 |
| 17 | 1 | BSY2: | — | BSY2 |
| 18 | 1 | CFGBSY: | — | Programming or erase configuration busy. |
Rejestr: CR 0x40022014
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Flash control register
| Bit | Szer. | Pole | Dostęp | Opis |
| 0 | 1 | PG: | — | Programming |
| 1 | 1 | PER: | — | Page erase |
| 2 | 1 | MER1: | — | Mass erase |
| 3–12 | 10 | PNB: | — | Page number |
| 13 | 1 | BKER: | — | BKER |
| 15 | 1 | MER2: | — | MER2 |
| 16 | 1 | STRT: | — | Start |
| 17 | 1 | OPTSTRT: | — | Options modification start |
| 18 | 1 | FSTPG: | — | Fast programming |
| 24 | 1 | EOPIE: | — | End of operation interrupt enable |
| 25 | 1 | ERRIE: | — | Error interrupt enable |
| 27 | 1 | OBL_LAUNCH: | — | Force the option byte loading |
| 30 | 1 | OPTLOCK: | — | Options Lock |
| 31 | 1 | LOCK: | — | FLASH_CR Lock |
Rejestr: ECCR: 0x40022018
Flash ECC register
| Bit | Szer. | Pole | Dostęp | Opis |
| 0–13 | 14 | ADDR_ECC | `ro` | ECC fail address |
| 20 | 1 | SYSF_ECC | `ro` | ECC fail for Corrected ECC Error or Double ECC Error in info block |
| 24 | 1 | ECCIE | `rw` | ECC correction interrupt enable |
| 30 | 1 | ECCC | `rw` | ECC correction |
| 31 | 1 | ECCD | `rw` | ECC detection |
Rejestr: OPTR 0x40022020
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Flash option register
| Bit | Szer. | Pole | Dostęp | Opis |
| 0–7 | 8 | RDP: | — | Read protection level |
| 13 | 1 | nRST_STOP: | — | nRST_STOP |
| 14 | 1 | nRST_STDBY: | — | nRST_STDBY |
| 16 | 1 | IWDG_SW: | — | Independent watchdog selection |
| 17 | 1 | IWDG_STOP: | — | Independent watchdog counter freeze in Stop mode |
| 18 | 1 | IWDG_STDBY: | — | Independent watchdog counter freeze in Standby mode |
| 19 | 1 | WWDG_SW: | — | Window watchdog selection |
| 20 | 1 | nSWAP_BANK: | — | nSWAP_BANK |
| 21 | 1 | DUAL_BANK: | — | DUAL_BANK |
| 22 | 1 | RAM_PARITY_CHECK: | — | SRAM parity check control |
| 24 | 1 | nBOOT_SEL: | — | nBOOT_SEL |
| 25 | 1 | nBOOT1: | — | Boot configuration |
| 26 | 1 | nBOOT0: | — | nBOOT0 option bit |
Rejestr: WRP1AR 0x4002202C
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Flash WRP area A address register
| Bit | Szer. | Pole | Dostęp | Opis |
| 0–6 | 7 | WRP1A_STRT: | — | WRP area A start offset |
| 16–22 | 7 | WRP1A_END: | — | WRP area A end offset |
Rejestr: WRP1BR 0x40022030
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Flash WRP area B address register
| Bit | Szer. | Pole | Dostęp | Opis |
| 0–6 | 7 | WRP1B_STRT: | — | WRP area B start offset |
| 16–22 | 7 | WRP1B_END: | — | WRP area B end offset |
Rejestr: WRP2AR 0x4002204C
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FLASH WRP2 area A address register
| Bit | Szer. | Pole | Dostęp | Opis |
| 0–6 | 7 | WRP2A_STRT: | — | WRP2A_STRT |
| 16–22 | 7 | WRP2A_END: | — | WRP2A_END |
Rejestr: WRP2BR 0x40022050
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FLASH WRP2 area B address register
| Bit | Szer. | Pole | Dostęp | Opis |
| 0–6 | 7 | WRP2B_STRT: | — | WRP2B_STRT |
| 16–22 | 7 | WRP2B_END: | — | WRP2B_END |