System
EXTI 0x40021800
11 rejestrów/klastrów w tym peryferium.
Rejestr: RTSR1 0x40021800
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EXTI rising trigger selection register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|---|---|---|---|
| 0 | 1 | RT0: | — | Rising trigger event configuration bit of Configurable Event line |
| 1 | 1 | RT1: | — | Rising trigger event configuration bit of Configurable Event line |
| 2 | 1 | RT2: | — | Rising trigger event configuration bit of Configurable Event line |
| 3 | 1 | RT3: | — | Rising trigger event configuration bit of Configurable Event line |
| 4 | 1 | RT4: | — | Rising trigger event configuration bit of Configurable Event line |
| 5 | 1 | RT5: | — | Rising trigger event configuration bit of Configurable Event line |
| 6 | 1 | RT6: | — | Rising trigger event configuration bit of Configurable Event line |
| 7 | 1 | RT7: | — | Rising trigger event configuration bit of Configurable Event line |
| 8 | 1 | RT8: | — | Rising trigger event configuration bit of Configurable Event line |
| 9 | 1 | RT9: | — | Rising trigger event configuration bit of Configurable Event line |
| 10 | 1 | RT10: | — | Rising trigger event configuration bit of Configurable Event line |
| 11 | 1 | RT11: | — | Rising trigger event configuration bit of Configurable Event line |
| 12 | 1 | RT12: | — | Rising trigger event configuration bit of Configurable Event line |
| 13 | 1 | RT13: | — | Rising trigger event configuration bit of Configurable Event line |
| 14 | 1 | RT14: | — | Rising trigger event configuration bit of Configurable Event line |
| 15 | 1 | RT15: | — | Rising trigger event configuration bit of Configurable Event line |
Rejestr: FTSR1 0x40021804
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EXTI falling trigger selection register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|---|---|---|---|
| 0 | 1 | FT0: | — | Falling trigger event configuration bit of configurable line |
| 1 | 1 | FT1: | — | Falling trigger event configuration bit of configurable line |
| 2 | 1 | FT2: | — | Falling trigger event configuration bit of configurable line |
| 3 | 1 | FT3: | — | Falling trigger event configuration bit of configurable line |
| 4 | 1 | FT4: | — | Falling trigger event configuration bit of configurable line |
| 5 | 1 | FT5: | — | Falling trigger event configuration bit of configurable line |
| 6 | 1 | FT6: | — | Falling trigger event configuration bit of configurable line |
| 7 | 1 | FT7: | — | Falling trigger event configuration bit of configurable line |
| 8 | 1 | FT8: | — | Falling trigger event configuration bit of configurable line |
| 9 | 1 | FT9: | — | Falling trigger event configuration bit of configurable line |
| 10 | 1 | FT10: | — | Falling trigger event configuration bit of configurable line |
| 11 | 1 | FT11: | — | Falling trigger event configuration bit of configurable line |
| 12 | 1 | FT12: | — | Falling trigger event configuration bit of configurable line |
| 13 | 1 | FT13: | — | Falling trigger event configuration bit of configurable line |
| 14 | 1 | FT14: | — | Falling trigger event configuration bit of configurable line |
| 15 | 1 | FT15: | — | Falling trigger event configuration bit of configurable line |
Rejestr: SWIER1 0x40021808
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EXTI software interrupt event register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|---|---|---|---|
| 0 | 1 | SWI0: | — | Software rising edge event trigger on line |
| 1 | 1 | SWI1: | — | Software rising edge event trigger on line |
| 2 | 1 | SWI2: | — | Software rising edge event trigger on line |
| 3 | 1 | SWI3: | — | Software rising edge event trigger on line |
| 4 | 1 | SWI4: | — | Software rising edge event trigger on line |
| 5 | 1 | SWI5: | — | Software rising edge event trigger on line |
| 6 | 1 | SWI6: | — | Software rising edge event trigger on line |
| 7 | 1 | SWI7: | — | Software rising edge event trigger on line |
| 8 | 1 | SWI8: | — | Software rising edge event trigger on line |
| 9 | 1 | SWI9: | — | Software rising edge event trigger on line |
| 10 | 1 | SWI10: | — | Software rising edge event trigger on line |
| 11 | 1 | SWI11: | — | Software rising edge event trigger on line |
| 12 | 1 | SWI12: | — | Software rising edge event trigger on line |
| 13 | 1 | SWI13: | — | Software rising edge event trigger on line |
| 14 | 1 | SWI14: | — | Software rising edge event trigger on line |
| 15 | 1 | SWI15: | — | Software rising edge event trigger on line |
Rejestr: RPR1 0x4002180C
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EXTI rising edge pending register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|---|---|---|---|
| 0 | 1 | RPIF0: | — | Rising edge event pending for configurable line |
| 1 | 1 | RPIF1: | — | Rising edge event pending for configurable line |
| 2 | 1 | RPIF2: | — | Rising edge event pending for configurable line |
| 3 | 1 | RPIF3: | — | Rising edge event pending for configurable line |
| 4 | 1 | RPIF4: | — | Rising edge event pending for configurable line |
| 5 | 1 | RPIF5: | — | configurable event inputs x rising edge Pending bit |
| 6 | 1 | RPIF6: | — | Rising edge event pending for configurable line |
| 7 | 1 | RPIF7: | — | Rising edge event pending for configurable line |
| 8 | 1 | RPIF8: | — | Rising edge event pending for configurable line |
| 9 | 1 | RPIF9: | — | Rising edge event pending for configurable line |
| 10 | 1 | RPIF10: | — | Rising edge event pending for configurable line |
| 11 | 1 | RPIF11: | — | Rising edge event pending for configurable line |
| 12 | 1 | RPIF12: | — | Rising edge event pending for configurable line |
| 13 | 1 | RPIF13: | — | Rising edge event pending for configurable line |
| 14 | 1 | RPIF14: | — | Rising edge event pending for configurable line |
| 15 | 1 | RPIF15: | — | Rising edge event pending for configurable line |
Rejestr: FPR1 0x40021810
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EXTI falling edge pending register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|---|---|---|---|
| 0 | 1 | FPIF0: | — | Falling edge event pending for configurable line |
| 1 | 1 | FPIF1: | — | Falling edge event pending for configurable line |
| 2 | 1 | FPIF2: | — | Falling edge event pending for configurable line |
| 3 | 1 | FPIF3: | — | Falling edge event pending for configurable line |
| 4 | 1 | FPIF4: | — | Falling edge event pending for configurable line |
| 5 | 1 | FPIF5: | — | Falling edge event pending for configurable line |
| 6 | 1 | FPIF6: | — | Falling edge event pending for configurable line |
| 7 | 1 | FPIF7: | — | Falling edge event pending for configurable line |
| 8 | 1 | FPIF8: | — | Falling edge event pending for configurable line |
| 9 | 1 | FPIF9: | — | Falling edge event pending for configurable line |
| 10 | 1 | FPIF10: | — | Falling edge event pending for configurable line |
| 11 | 1 | FPIF11: | — | Falling edge event pending for configurable line |
| 12 | 1 | FPIF12: | — | Falling edge event pending for configurable line |
| 13 | 1 | FPIF13: | — | Falling edge event pending for configurable line |
| 14 | 1 | FPIF14: | — | Falling edge event pending for configurable line |
| 15 | 1 | FPIF15: | — | Falling edge event pending for configurable line |
Rejestr: EXTICR1 0x40021860
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EXTI external interrupt selection register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|---|---|---|---|
| 0–7 | 8 | EXTI0: | — | GPIO port selection |
| 8–15 | 8 | EXTI1 | — | GPIO port selection |
| 16–23 | 8 | EXTI2 | — | GPIO port selection |
| 24–31 | 8 | EXTI3 | — | GPIO port selection |
Rejestr: EXTICR2 0x40021864
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EXTI external interrupt selection register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|---|---|---|---|
| 0–7 | 8 | EXTI4 | — | GPIO port selection |
| 8–15 | 8 | EXTI5 | — | GPIO port selection |
| 16–23 | 8 | EXTI6 | — | GPIO port selection |
| 24–31 | 8 | EXTI7 | — | GPIO port selection |
Rejestr: EXTICR3 0x40021868
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EXTI external interrupt selection register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|---|---|---|---|
| 0–7 | 8 | EXTI8 | — | GPIO port selection |
| 8–15 | 8 | EXTI9 | — | GPIO port selection |
| 16–23 | 8 | EXTI10 | — | GPIO port selection |
| 24–31 | 8 | EXTI11 | — | GPIO port selection |
Rejestr: EXTICR4 0x4002186C
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EXTI external interrupt selection register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|---|---|---|---|
| 0–7 | 8 | EXTI12 | — | GPIO port selection |
| 8–15 | 8 | EXTI13 | — | GPIO port selection |
| 16–23 | 8 | EXTI14 | — | GPIO port selection |
| 24–31 | 8 | EXTI15 | — | GPIO port selection |
Rejestr: IMR1 0x40021880
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EXTI CPU wakeup with interrupt mask register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|---|---|---|---|
| 0 | 1 | IM0: | — | CPU wakeup with interrupt mask on event input |
| 1 | 1 | IM1: | — | CPU wakeup with interrupt mask on event input |
| 2 | 1 | IM2: | — | CPU wakeup with interrupt mask on event input |
| 3 | 1 | IM3: | — | CPU wakeup with interrupt mask on event input |
| 4 | 1 | IM4: | — | CPU wakeup with interrupt mask on event input |
| 5 | 1 | IM5: | — | CPU wakeup with interrupt mask on event input |
| 6 | 1 | IM6: | — | CPU wakeup with interrupt mask on event input |
| 7 | 1 | IM7: | — | CPU wakeup with interrupt mask on event input |
| 8 | 1 | IM8: | — | CPU wakeup with interrupt mask on event input |
| 9 | 1 | IM9: | — | CPU wakeup with interrupt mask on event input |
| 10 | 1 | IM10: | — | CPU wakeup with interrupt mask on event input |
| 11 | 1 | IM11: | — | CPU wakeup with interrupt mask on event input |
| 12 | 1 | IM12: | — | CPU wakeup with interrupt mask on event input |
| 13 | 1 | IM13: | — | CPU wakeup with interrupt mask on event input |
| 14 | 1 | IM14: | — | CPU wakeup with interrupt mask on event input |
| 15 | 1 | IM15: | — | CPU wakeup with interrupt mask on event input |
| 19 | 1 | IM19: | — | CPU wakeup with interrupt mask on event input |
| 21 | 1 | IM21: | — | CPU wakeup with interrupt mask on event input |
| 22 | 1 | IM22: | — | CPU wakeup with interrupt mask on event input |
| 23 | 1 | IM23: | — | CPU wakeup with interrupt mask on event input |
| 24 | 1 | IM24: | — | CPU wakeup with interrupt mask on event input |
| 25 | 1 | IM25: | — | CPU wakeup with interrupt mask on event input |
| 26 | 1 | IM26: | — | CPU wakeup with interrupt mask on event input |
| 31 | 1 | IM31: | — | CPU wakeup with interrupt mask on event input |
Rejestr: EMR1 0x40021884
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EXTI CPU wakeup with event mask register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|---|---|---|---|
| 0 | 1 | EM0: | — | CPU wakeup with event mask on event input |
| 1 | 1 | EM1: | — | CPU wakeup with event mask on event input |
| 2 | 1 | EM2: | — | CPU wakeup with event mask on event input |
| 3 | 1 | EM3: | — | CPU wakeup with event mask on event input |
| 4 | 1 | EM4: | — | CPU wakeup with event mask on event input |
| 5 | 1 | EM5: | — | CPU wakeup with event mask on event input |
| 6 | 1 | EM6: | — | CPU wakeup with event mask on event input |
| 7 | 1 | EM7: | — | CPU wakeup with event mask on event input |
| 8 | 1 | EM8: | — | CPU wakeup with event mask on event input |
| 9 | 1 | EM9: | — | CPU wakeup with event mask on event input |
| 10 | 1 | EM10: | — | CPU wakeup with event mask on event input |
| 11 | 1 | EM11: | — | CPU wakeup with event mask on event input |
| 12 | 1 | EM12: | — | CPU wakeup with event mask on event input |
| 13 | 1 | EM13: | — | CPU wakeup with event mask on event input |
| 14 | 1 | EM14: | — | CPU wakeup with event mask on event input |
| 15 | 1 | EM15: | — | CPU wakeup with event mask on event input |
| 19 | 1 | EM19: | — | CPU wakeup with event mask on event input |
| 21 | 1 | EM21: | — | CPU wakeup with event mask on event input |
| 23 | 1 | EM23: | — | CPU wakeup with event mask on event input |
| 25 | 1 | EM25: | — | CPU wakeup with event mask on event input |
| 26 | 1 | EM26: | — | CPU wakeup with event mask on event input |
| 31 | 1 | EM31: | — | CPU wakeup with event mask on event input |