System
SYSCFG 0x40010000
2 rejestrów/klastrów w tym peryferium.
Rejestr: CFGR1 0x40010000
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SYSCFG configuration register 1
| Bit | Szer. | Pole | Dostęp | Opis |
|---|---|---|---|---|
| 0–1 | 2 | MEM_MODE: | — | Memory mapping selection bits |
| 3 | 1 | PA11_RMP: | — | PA11_RMP |
| 4 | 1 | PA12_RMP: | — | PA11 and PA12 remapping bit. |
| 5 | 1 | IR_POL: | — | IR output polarity selection |
| 6–7 | 2 | IR_MOD: | — | IR Modulation Envelope signal selection. |
| 8 | 1 | BOOSTEN: | — | I/O analog switch voltage booster enable |
| 9 | 1 | UCPD1_STROBE: | — | Strobe signal bit for UCPD1 |
| 10 | 1 | UCPD2_STROBE: | — | Strobe signal bit for UCPD2 |
| 16 | 1 | I2C_PBx_FMP: | — | Fast Mode Plus (FM+) driving capability activation bits |
| 17 | 1 | I2C_PB7_FMP: | — | I2C_PB7_FMP |
| 18 | 1 | I2C_PB8_FMP: | — | I2C_PB8_FMP |
| 19 | 1 | I2C_PB9_FMP: | — | I2C_PB9_FMP |
| 20 | 1 | I2C1_FMP: | — | FM+ driving capability activation for I2C1 |
| 21 | 1 | I2C2_FMP: | — | FM+ driving capability activation for I2C2 |
| 22 | 1 | I2C_PA9_FMP: | — | Fast Mode Plus (FM+) driving capability activation bits |
| 23 | 1 | I2C_PA10_FMP: | — | Fast Mode Plus (FM+) driving capability activation bits |
| 24 | 1 | I2C3_FMP: | — | I2C3_FMP |
Rejestr: CFGR2 0x40010018
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SYSCFG configuration register 1
| Bit | Szer. | Pole | Dostęp | Opis |
|---|---|---|---|---|
| 0 | 1 | LOCKUP_LOCK: | — | Cortex-M0+ LOCKUP bit enable bit |
| 1 | 1 | SRAM_PARITY_LOCK: | — | SRAM parity lock bit |
| 3 | 1 | ECC_LOCK: | — | ECC error lock bit |
| 8 | 1 | SRAM_PEF: | — | SRAM parity error flag |