RTC / Watchdog

RTC 0x40002800

20 rejestrów/klastrów w tym peryferium.

Rejestr: TR: 0x40002800

RTC time register

Bit	Szer.	Pole	Dostęp	Opis
0–3	4	SU	`rw`	Second units in BCD format
4–6	3	ST	`rw`	Second tens in BCD format
8–11	4	MNU	`rw`	Minute units in BCD format
12–14	3	MNT	`rw`	Minute tens in BCD format
16–19	4	HU	`rw`	Hour units in BCD format
20–21	2	HT	`rw`	Hour tens in BCD format
22	1	PM	`rw`	AM/PM notation

Rejestr: DR: 0x40002804

RTC date register

Bit	Szer.	Pole	Dostęp	Opis
0–3	4	DU	`rw`	Date units in BCD format
4–5	2	DT	`rw`	Date tens in BCD format
8–11	4	MU	`rw`	Month units in BCD format
12	1	MT	`rw`	Month tens in BCD format
13–15	3	WDU	`rw`	Week day units ...
16–19	4	YU	`rw`	Year units in BCD format
20–23	4	YT	`rw`	Year tens in BCD format

Rejestr: SSR: 0x40002808

RTC sub second register

Bit	Szer.	Pole	Dostęp	Opis
0–15	16	SS	`ro`	Sub second value SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below: Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1) Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR.

Rejestr: ICSR: 0x4000280C

RTC initialization control and status register

Bit	Szer.	Pole	Dostęp	Opis
0	1	ALRAWF	`ro`	Alarm A write flag
1	1	ALRBWF	`ro`	Alarm B write flag
2	1	WUTWF	`ro`	Wakeup timer write flag This bit is set by hardware when WUT value can be changed, after the WUTE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode.
3	1	SHPF	`ro`	Shift operation pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect.
4	1	INITS	`ro`	Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (Backup domain reset state).
5	1	RSF	`rw`	Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSR, RTC_TR and RTC_DR). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF = 1), or when in bypass shadow register mode (BYPSHAD = 1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode.
6	1	INITF	`ro`	Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated.
7	1	INIT	`rw`	Initialization mode
16	1	RECALPF	`ro`	Recalibration pending Flag The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. Refer to .

Rejestr: PRER: 0x40002810

RTC prescaler register

Bit	Szer.	Pole	Dostęp	Opis
0–14	15	PREDIV_S	`rw`	Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1)
16–22	7	PREDIV_A	`rw`	Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)

Rejestr: WUTR: 0x40002814

RTC wakeup timer register

Bit	Szer.	Pole	Dostęp	Opis
0–15	16	WUT	`rw`	Wakeup auto-reload value bits When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0]+1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register. When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. The first assertion of WUTF occurs between WUT and (WUT + 1) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] = 011 (RTCCLK/2) is forbidden.

Rejestr: CR: 0x40002818

control register

Bit	Szer.	Pole	Dostęp	Opis
0–2	3	WUCKSEL	`rw`	ck_wut wakeup clock selection 10x: ck_spre (usually 1Hz) clock is selected 11x: ck_spre (usually 1Hz) clock is selected and 216is added to the WUT counter value
3	1	TSEDGE	`rw`	Timestamp event active edge TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting.
4	1	REFCKON	`rw`	RTC_REFIN reference clock detection enable (50 or 60Hz) Note: PREDIV_S must be 0x00FF.
5	1	BYPSHAD	`rw`	Bypass the shadow registers Note: If the frequency of the APB1 clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1.
6	1	FMT	`rw`	Hour format
8	1	ALRAE	`rw`	Alarm A enable
9	1	ALRBE	`rw`	Alarm B enable
10	1	WUTE	`rw`	Wakeup timer enable Note: When the wakeup timer is disabled, wait for WUTWF=1 before enabling it again.
11	1	TSE	`rw`	timestamp enable
12	1	ALRAIE	`rw`	Alarm A interrupt enable
13	1	ALRBIE	`rw`	Alarm B interrupt enable
14	1	WUTIE	`rw`	Wakeup timer interrupt enable
15	1	TSIE	`rw`	Timestamp interrupt enable
16	1	ADD1H	`wo`	Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0.
17	1	SUB1H	`wo`	Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0.
18	1	BKP	`rw`	Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not.
19	1	COSEL	`rw`	Calibration output selection When COE = 1, this bit selects which signal is output on CALIB. These frequencies are valid for RTCCLK at 32.768kHz and prescalers at their default values (PREDIV_A = 127 and PREDIV_S = 255). Refer to .
20	1	POL	`rw`	Output polarity This bit is used to configure the polarity of TAMPALRM output.
21–22	2	OSEL	`rw`	Output selection These bits are used to select the flag to be routed to TAMPALRM output.
23	1	COE	`rw`	Calibration output enable This bit enables the CALIB output
24	1	ITSE	`rw`	timestamp on internal event enable
25	1	TAMPTS	`rw`	Activate timestamp on tamper detection event TAMPTS is valid even if TSE = 0 in the RTC_CR register. Timestamp flag is set after the tamper flags, therefore if TAMPTS and TSIE are set, it is recommended to disable the tamper interrupts in order to avoid servicing 2 interrupts.
26	1	TAMPOE	`rw`	Tamper detection output enable on TAMPALRM
29	1	TAMPALRM_PU	`rw`	TAMPALRM pull-up enable
30	1	TAMPALRM_TYPE	`rw`	TAMPALRM output type
31	1	OUT2EN	`rw`	RTC_OUT2 output enable Setting this bit allows to remap the RTC outputs on RTC_OUT2 as follows: OUT2EN = 0: RTC output 2 disable If OSEL different 00 or TAMPOE = 1: TAMPALRM is output on RTC_OUT1 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT1 OUT2EN = 1: RTC output 2 enable If (OSEL different 00 or TAMPOE = 1) and COE = 0: TAMPALRM is output on RTC_OUT2 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT2 If (OSEL different 00 or TAMPOE = 1) and COE = 1: CALIB is output on RTC_OUT2 and TAMPALRM is output on RTC_OUT1.

Rejestr: WPR: 0x40002824

write protection register

Bit	Szer.	Pole	Dostęp	Opis
0–7	8	KEY	`wo`	Write protection key This byte is written by software. Reading this byte always returns 0x00. Refer to for a description of how to unlock RTC register write protection.

Rejestr: CALR: 0x40002828

RTC calibration register

Bit	Szer.	Pole	Dostęp	Opis
0–8	9	CALM	`rw`	Calibration minus The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768Hz). This decreases the frequency of the calendar with a resolution of 0.9537ppm. To increase the frequency of the calendar, this feature should be used in conjunction with CALP. See .
13	1	CALW16	`rw`	Use a 16-second calibration cycle period When CALW16 is set to 1, the 16-second calibration cycle period is selected. This bit must not be set to 1 if CALW8 = 1. Note: CALM[0] is stuck at 0 when CALW16 = 1. Refer to calibration.
14	1	CALW8	`rw`	Use an 8-second calibration cycle period When CALW8 is set to 1, the 8-second calibration cycle period is selected. Note: CALM[1:0] are stuck at 00 when CALW8 = 1. Refer to digital calibration.
15	1	CALP	`rw`	Increase frequency of RTC by 488

Rejestr: SHIFTR: 0x4000282C

RTC shift control register

Bit	Szer.	Pole	Dostęp	Opis
0–14	15	SUBFS	`wo`	Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / (PREDIV_S + 1) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF = 1 to be sure that the shadow registers have been updated with the shifted time.
31	1	ADD1S	`wo`	Add one second This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation.

Rejestr: TSTR 0x40002830

RTC timestamp time register

Brak zdefiniowanych pól bitowych.

Rejestr: TSDR 0x40002834

RTC timestamp date register

Brak zdefiniowanych pól bitowych.

Rejestr: TSSSR 0x40002838

RTC timestamp sub second register

Brak zdefiniowanych pól bitowych.

Rejestr: ALRMAR: 0x40002840

Alarm A register

Bit	Szer.	Pole	Dostęp	Opis
0–3	4	SU	`rw`	Second units in BCD format
4–6	3	ST	`rw`	Second tens in BCD format
7	1	MSK1	`rw`	Alarm seconds mask
8–11	4	MNU	`rw`	Minute units in BCD format
12–14	3	MNT	`rw`	Minute tens in BCD format
15	1	MSK2	`rw`	Alarm minutes mask
16–19	4	HU	`rw`	Hour units in BCD format
20–21	2	HT	`rw`	Hour tens in BCD format
22	1	PM	`rw`	AM/PM notation
23	1	MSK3	`rw`	Alarm hours mask
24–27	4	DU	`rw`	Date units or day in BCD format
28–29	2	DT	`rw`	Date tens in BCD format
30	1	WDSEL	`rw`	Week day selection
31	1	MSK4	`rw`	Alarm date mask

Rejestr: ALRMASSR: 0x40002844

Alarm A sub-second register

Bit	Szer.	Pole	Dostęp	Opis
0–14	15	SS	`rw`	Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if alarm A is to be activated. Only bits 0 up MASKSS-1 are compared.
24–27	4	MASKSS	`rw`	Mask the most-significant bits starting at this bit 2: SS[14:2] are don't care in alarm A comparison. Only SS[1:0] are compared. 3: SS[14:3] are don't care in alarm A comparison. Only SS[2:0] are compared. ... 12: SS[14:12] are don't care in alarm A comparison. SS[11:0] are compared. 13: SS[14:13] are don't care in alarm A comparison. SS[12:0] are compared. 14: SS[14] is don't care in alarm A comparison. SS[13:0] are compared. 15: All 15 SS bits are compared and must match to activate alarm. The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. Note: The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation.

Rejestr: ALRMBR: 0x40002848

Alarm B register

Bit	Szer.	Pole	Dostęp	Opis
0–3	4	SU	`rw`	Second units in BCD format
4–6	3	ST	`rw`	Second tens in BCD format
7	1	MSK1	`rw`	Alarm seconds mask
8–11	4	MNU	`rw`	Minute units in BCD format
12–14	3	MNT	`rw`	Minute tens in BCD format
15	1	MSK2	`rw`	Alarm minutes mask
16–19	4	HU	`rw`	Hour units in BCD format
20–21	2	HT	`rw`	Hour tens in BCD format
22	1	PM	`rw`	AM/PM notation
23	1	MSK3	`rw`	Alarm hours mask
24–27	4	DU	`rw`	Date units or day in BCD format
28–29	2	DT	`rw`	Date tens in BCD format
30	1	WDSEL	`rw`	Week day selection
31	1	MSK4	`rw`	Alarm date mask

Rejestr: ALRMBSSR: 0x4000284C

Alarm B sub-second register

Bit	Szer.	Pole	Dostęp	Opis
0–14	15	SS	`rw`	Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if alarm A is to be activated. Only bits 0 up MASKSS-1 are compared.
24–27	4	MASKSS	`rw`	Mask the most-significant bits starting at this bit 2: SS[14:2] are don't care in alarm A comparison. Only SS[1:0] are compared. 3: SS[14:3] are don't care in alarm A comparison. Only SS[2:0] are compared. ... 12: SS[14:12] are don't care in alarm A comparison. SS[11:0] are compared. 13: SS[14:13] are don't care in alarm A comparison. SS[12:0] are compared. 14: SS[14] is don't care in alarm A comparison. SS[13:0] are compared. 15: All 15 SS bits are compared and must match to activate alarm. The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. Note: The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation.

Rejestr: SR: 0x40002850

RTC status register

Bit	Szer.	Pole	Dostęp	Opis
0	1	ALRAF	`ro`	Alarm A flag
1	1	ALRBF	`ro`	Alarm B flag
2	1	WUTF	`ro`	Wakeup timer flag This flag is set by hardware when the wakeup auto-reload counter reaches 0. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again.
3	1	TSF	`ro`	Timestamp flag This flag is set by hardware when a timestamp event occurs. If ITSF flag is set, TSF must be cleared together with ITSF.
4	1	TSOVF	`ro`	Timestamp overflow flag This flag is set by hardware when a timestamp event occurs while TSF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared.
5	1	ITSF	`ro`	Internal timestamp flag This flag is set by hardware when a timestamp on the internal event occurs.

Rejestr: MISR: 0x40002854

RTC masked interrupt status register

Bit	Szer.	Pole	Dostęp	Opis
0	1	ALRAMF	`ro`	Alarm A masked flag
1	1	ALRBMF	`ro`	Alarm B masked flag
2	1	WUTMF	`ro`	Wakeup timer masked flag This flag is set by hardware when the wakeup timer interrupt occurs. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again.
3	1	TSMF	`ro`	Timestamp masked flag This flag is set by hardware when a timestamp interrupt occurs. If ITSF flag is set, TSF must be cleared together with ITSF.
4	1	TSOVMF	`ro`	Timestamp overflow masked flag This flag is set by hardware when a timestamp interrupt occurs while TSMF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared.
5	1	ITSMF	`ro`	Internal timestamp masked flag This flag is set by hardware when a timestamp on the internal event occurs and timestampinterrupt is raised.

Rejestr: SCR: 0x4000285C

RTC status clear register

Bit	Szer.	Pole	Dostęp	Opis
0	1	CALRAF	`wo`	Clear alarm A flag Writing 1 in this bit clears the ALRAF bit in the RTC_SR register.
1	1	CALRBF	`wo`	Clear alarm B flag Writing 1 in this bit clears the ALRBF bit in the RTC_SR register.
2	1	CWUTF	`wo`	Clear wakeup timer flag Writing 1 in this bit clears the WUTF bit in the RTC_SR register.
3	1	CTSF	`wo`	Clear timestamp flag Writing 1 in this bit clears the TSOVF bit in the RTC_SR register. If ITSF flag is set, TSF must be cleared together with ITSF by setting CRSF and CITSF.
4	1	CTSOVF	`wo`	Clear timestamp overflow flag Writing 1 in this bit clears the TSOVF bit in the RTC_SR register. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared.
5	1	CITSF	`wo`	Clear internal timestamp flag Writing 1 in this bit clears the ITSF bit in the RTC_SR register.